STemWin connection to project (example for STM32F429 for Keil project)

https://github.com/golf2109/STM32F429ZI_SSD1963_FT5336/

 Add STemWin library to project/
Download from st.com STemWin library packet (exapmle STemWin_Library_V1.2.0).
Package content
This version of the STemWin Library package contains the following sub folders:
Config: contains configuration files for the library and LCD drivers
Documentation: contains emWin "User & Reference Guide"
inc: contains header files of the library components
Lib: contains the Library GUI in object format (.a and .lib), running on all STM32 devices based on CortexM0, CortexM3, CortexM4F or CortexM7 cores, all with and without OS support. The naming format is STemWinv_CMx_YY_C_ot.a, where
v: STemWin version (ex. v=522)
x : the CMx core class (CM0, CM3, CM4 or CM7)
YY: OS support

C: compiler (IAR, Keil, GCC)
ot: binary generated with high speed optimization
OS: contains library interface with RTOS
Simulation: contains system resources for WIN32 in precompiled library format

Software: contains software tools (Bitmap Converter, Font Converter, GUIBuilder, JPEG2Movie and emVNC)

Add to project folder EmWin and copy file STemWin532_CM4_Keil.lib from \STemWin_Library_V1.2.0\Libraries\STemWinLibrary532\Lib to this folder.

Copy folder inc from \STemWin_Library_V1.2.0\Libraries\STemWinLibrary532 to the project.
 Add config file from \STemWin_Library_V1.2.0\Libraries\STemWinLibrary532\Config fo folder EmWin in project
GUIConf.c
GUIConf.h
LCDConf_FlexColor_Template.c
LCDConf_FlexColor_Template.h
Rename LCDConf_FlexColor_Template.c  &  LCDConf_FlexColor_Template.h  to LCDConf_FlexColor.c  &  LCDConf_FlexColor.h.
Add file \STemWin_Library_V1.2.0\Libraries\STemWinLibrary532\OS\GUI_X.c to the project

Add include patch in Option for target for EmWin folder & EmWin\inc subfolder. Delete read only attribute from files GUI_X.c, GUIConf.c, LCDConf_Flex_color.c (example for GUI_X.c)

Add #include GUI.h to main.c. Add init procedure   GUI_Init(); to main.c. In file GUIConf.c decrease memory for GUI from 0x200000:

to 0x20000:

Compile project. All must be OK.

In the file LCDConf_Flex_color.c set for our display size set

Add in fincshion LcdWriteReg, LcdWriteData, LcdWriteMultiple,  LcdReadMultiple  add command for our display connection:

In function LCD_X_Config rename driver for our display:

In main.c before string GUI_Init();  add string 

  __HAL_RCC_CRC_CLK_ENABLE();  

In file stm32f4xx_it.c add string 

extern volatile uint32_t OS_TimeMS;

in SysTick_Handler() add 

OS_TimeMS++;

SSD1963 Init collection

My Init file for SSD1963

void Init_SSD1963(void)
{
Lcd_Write_Cmd(0xe0); //START PLL
Lcd_Write_Data(0x01);  //Set bit Enable PLL
HAL_Delay(50);  //Wait  to let the PLL stable
 
Lcd_Write_Cmd(0xe0); //START PLL
Lcd_Write_Data(0x03);  //(0 - Use reference clock as system clock   1 -  Use PLL output as system clock)
HAL_Delay(5);

Lcd_Write_Cmd(0x01); // Software reset
HAL_Delay(10);
 
Lcd_Write_Cmd(0xe2);//Set the PLL
Lcd_Write_Data(0x1d);
Lcd_Write_Data(0x02);
Lcd_Write_Data(0x54);
 
Lcd_Write_Cmd(0xe6);//Set the LSHIFT (pixel clock) frequency
Lcd_Write_Data(0x04);
Lcd_Write_Data(0x6f);
Lcd_Write_Data(0x47);

Lcd_Write_Cmd(0xf0);//SET pixel data I/F format=8bit
Lcd_Write_Data(0x03); //pixel data format, 0x03 is 16bit(565 format);0x00 is for 8-bit

Lcd_Write_Cmd(0xb0); //LCD SPECIFICATION   SET LCD MODE SET TFT 18Bits MODE
Lcd_Write_Data(0x20);  //dput(0x08); //SET TFT MODE & hsync+Vsync+DEN MODE
Lcd_Write_Data(0x80);  //
Lcd_Write_Data(0x03);//SET horizontal size=800-1 HightByte
Lcd_Write_Data(0x1f);//1f   //SET horizontal size=800-1 LowByte
Lcd_Write_Data(0x01);//SET vertical size=480-1 HightByte
Lcd_Write_Data(0xdf);//df   //SET vertical size=480-1 LowByte
Lcd_Write_Data(0x00);//   dput(0x2d); //SET even/odd line RGB seq.=RGB

//Set front porch and back porch
Lcd_Write_Cmd(0xb4);// SET HBP
Lcd_Write_Data(0x04); // SET HSYNC Total = // 0x04 SET HSYNC Total = 1056  // hsync of  value in app note is 8367 & not 1056
Lcd_Write_Data(0x20);
Lcd_Write_Data(0x00); // SET HBP = //SET HBP = 256 // HBP of value in app note is 163 & not 256
Lcd_Write_Data(0x2e);  //SET VBP 0 //  earlier value of VBP = 8 , write data ( 0x07)
Lcd_Write_Data(0xd2);// SET VBP
Lcd_Write_Data(0x00);
Lcd_Write_Data(0x00);// SET Hsync pulse start position
Lcd_Write_Data(0x00);// SET Hsync pulse subpixel start position

Lcd_Write_Cmd(0xb6);    //SET VBP,
Lcd_Write_Data(0x02); //0x02 SET Vsync total 526 = 525 + 1  // vsync of  value in app note is 496  & not 525
Lcd_Write_Data(0x0d);
Lcd_Write_Data(0x00); //SET VBP = 45                // HBP of value in app note is 4 & not 45
Lcd_Write_Data(0x17);// 0x2d
Lcd_Write_Data(0x16);// 0x00 SET Vsync pulse 0     // SET Vsync pulse in app note is 2
Lcd_Write_Data(0x00); //SET Vsync pulse start position
Lcd_Write_Data(0x00);

Lcd_Write_Cmd(0x2a);    //SET column address
Lcd_Write_Data(0x00); //SET start column address=0
Lcd_Write_Data(0x00);
Lcd_Write_Data(0x03); //SET end column address=799
Lcd_Write_Data(0x1f);

Lcd_Write_Cmd(0x2b);;     //SET page address
Lcd_Write_Data(0x00);//SET start page address=0
Lcd_Write_Data(0x00);
Lcd_Write_Data(0x01);//SET end page address=479
Lcd_Write_Data(0xdf);  //1f

Lcd_Write_Cmd(0x036);  //SET RGB BGR
Lcd_Write_Data(0x08);  //1 BGR  0  RGB

Lcd_Write_Cmd(0xb8);
Lcd_Write_Data(0x0f);
Lcd_Write_Data(0x01);

Lcd_Write_Cmd(0xba);
Lcd_Write_Data(0x01);

Lcd_Write_Cmd(0x29);// SET display on

Lcd_Write_Cmd(0x2c);
} 

 // Horizontal and vertical display resolution (from the glass datasheet)
  #define DISP_HOR_RESOLUTION  800
 #define DISP_VER_RESOLUTION   480

  // Horizontal synchronization timing in pixels (from the glass datasheet)
  #define DISP_HOR_PULSE_WIDTH 48   // 1..48 (Min .. Typ)
  #define DISP_HOR_BACK_PORCH 40  // Typ
  #define DISP_HOR_FRONT_PORCH 40  // Typ

  // Vertical synchronization timing in lines (from the glass datasheet)
  #define DISP_VER_PULSE_WIDTH 3   // Typ
  #define DISP_VER_BACK_PORCH 29 // Typ
  #define DISP_VER_FRONT_PORCH 13  // Typ


// *****************************************************************************
// Инициализация контроллера SSD1963 for PCLK, HSYNC, VSYNC etc
void SSD1963_Init(void)
{
  // Програмный сброс
  set_reg(0x01); // Soft reset (Сбрасываются все регистры кроме 0xE0 и 0xE5)
  LCD_Delay(5); // Нужно ожидать 5 мс
  
  // * Настройка PLL на 100 МГц перед его включением (для фнешего кыарца 10 МГц) *
  // Установка множителя M для PLL: VCO = crystal freq * (N+1) (где - 250MHz < VCO < 800MHz)
  // Частота PLL = VCO/M, макс 110MHz. 
  set_reg(0xE2);  // Уст. PLL для OSC = 10MHz
  set_data(0x1D); // Множитель N = 29, VCO (>250MHz)= OSC*(N+1), VCO = 300MHz
  set_data(0x02); // Делитель M = 2, PLL = 300/(M+1) = 100MHz
  set_data(0x04); // Установить использование M (множителя) и N (делителя) значений

  // * Запуск PLL *
  set_reg(0xE0); // Start PLL command
  set_data(0x01); // включить PLL
  LCD_Delay(1); // ожидание стабильности (100 мскек) минимум
  
  set_reg(0xE0); // Start PLL command again
  set_data(0x03); // Теперь PLL выход используя как системные часы
  LCD_Delay(1); // ожидание стабильности (100 мксек) минимум
  
  // Програмный сброс после включения PLL
  set_reg(0x01); // Soft reset
 LCD_Delay(10000);
  
  // Установить LSHIFT частоту, т.е DCLK для TFT если частота PLL 100 МГц set previously
  // Значение DCLK для HSD050IDW1-A20 равняется 33 МГц (по даташиту)
  // 33 MHz = 100MHz*(LCDC_FPR + 1)/2^20
  // LCDC_FPR = 346030 (0x547AE)
  // Time per line = (DISP_HOR_RESOLUTION + DISP_HOR_PULSE_WIDTH + DISP_HOR_BACK_PORCH +
  //                          DISP_HOR_FRONT_PORCH)/30.3 нсек = 928/30.3 = 30.6 нсек
  set_reg(0xE6);
  set_data(0x05);
  set_data(0x47);
  set_data(0xAE);  
  
  //Set panel mode, varies from individual manufacturer
  set_reg(0xB0);
// set_data(0x10); // set 18-bit for 7" panel TY700TFT800480
// set_data(0x80); // set TTL mode  
// set_data(0x08);  // SET TFT MODE & hsync + Vsync + DEN MODE
  set_data(0x20);  // set 24-bit 
  set_data(0x00);  // SET TFT MODE & hsync + Vsync + DEN MODE
  set_data(((DISP_HOR_RESOLUTION - 1) >> 8) & 0x0007);   // Set panel size
  set_data((DISP_HOR_RESOLUTION - 1) & 0x00FF);
  set_data(((DISP_VER_RESOLUTION - 1) >> 8) & 0x0007);
  set_data((DISP_VER_RESOLUTION - 1) & 0x00FF);
  set_data(0x00);  // RGB sequence

  // Set horizontal period
  set_reg(0xB4);
  #define HT (DISP_HOR_RESOLUTION + DISP_HOR_PULSE_WIDTH + DISP_HOR_BACK_PORCH + DISP_HOR_FRONT_PORCH)
  set_data(((HT - 1) >> 8) & 0x0007); // HT - horizontal total period
  set_data((HT - 1) & 0x00FF); // ...
  #define HPS (DISP_HOR_PULSE_WIDTH + DISP_HOR_BACK_PORCH)
  set_data(((HPS - 1) >> 8) & 0x0007); // HPS: Horizontal Sync Pulse Start Position
  set_data((HPS - 1) & 0x00FF); // ...
  set_data(DISP_HOR_PULSE_WIDTH - 1); // HPW: Horizontal Sync Pulse Width
  set_data(0x00); // LPS: Horizontal Display Period Start Position
  set_data(0x00); // ...
  set_data(0x00); // LPSPP: Horizontal Sync Pulse Subpixel Start Position
// (for serial TFT interface). Dummy value for TFT interface.
  // Set vertical period
  set_reg(0xB6);
  #define VT (DISP_VER_RESOLUTION + DISP_VER_PULSE_WIDTH + DISP_VER_BACK_PORCH +
            DISP_VER_FRONT_PORCH)  set_data(((VT - 1) >> 8) & 0x0007); // VT: Vertical Total   
  set_data((VT - 1) & 0x00FF); // ...
  #define VSP (DISP_VER_PULSE_WIDTH + DISP_VER_BACK_PORCH)
  set_data(((VSP - 1) >> 8) & 0x0007); // VPS: Vertical Sync Pulse Start Position
  set_data((VSP - 1) & 0x00FF); // ...
  set_data(DISP_VER_PULSE_WIDTH - 1); // VPW: Vertical Sync Pulse Width
  set_data(0x00); // FPS: Vertical Display Period Start Position
  set_data(0x00); // ...

  // SET Address mode 
  set_reg(0x36);
  set_data(0x00);  
//  set_data(0xA0);
//  set_data(0x03);  
  
  //Set pixel format, i.e. the bpp (команда была удалена см. даташит вер 1.1)
// set_reg(0x3A);
// set_data(0x50); // set 16bpp  

  // Set pixel data interface
  set_reg(0xF0);
  set_data(0x03); // 16-bit(565 format) data
  set_reg(0x29); // Turn on display; show the image on display
  LCD_Delay(5); // Нужно ожидать 5 мс  
  return;
}

=====================================================================

LCD_WriteCom(0x00E6); //PLL setting for PCLK, depends on resolution
LCD_WriteRAM(0x0003);
LCD_WriteRAM(0x00ff);
LCD_WriteRAM(0x00ff);

LCD_WriteCom(0x00B0); //LCD SPECIFICATION
/*LCD_WriteRAM(0x0027);
LCD_WriteRAM(0x0000);
LCD_WriteRAM((HDP>>8)&0X00FF);  //Set HDP
LCD_WriteRAM(HDP&0X00FF);
   LCD_WriteRAM((VDP>>8)&0X00FF);  //Set VDP
LCD_WriteRAM(VDP&0X00FF);
   LCD_WriteRAM(0x0000);*/
LCD_WriteRAM(0x0000);
LCD_WriteRAM(0x0004);  // 0x0000 18-bit mode
LCD_WriteRAM((HDP>>8)&0X00FF);  //Set HDP
LCD_WriteRAM(HDP&0X00FF);
   LCD_WriteRAM((VDP>>8)&0X00FF);  //Set VDP
LCD_WriteRAM(VDP&0X00FF);
   LCD_WriteRAM(0x0000);
   LCD_WriteCom(0x00B4); //HSYNC
LCD_WriteRAM((HT>>8)&0X00FF);  //Set HT
LCD_WriteRAM(HT&0X00FF);
LCD_WriteRAM((HPS>>8)&0X00FF);  //Set HPS
LCD_WriteRAM(HPS&0X00FF);
LCD_WriteRAM(HPW);   //Set HPW
LCD_WriteRAM((LPS>>8)&0X00FF);  //Set HPS
LCD_WriteRAM(LPS&0X00FF);
LCD_WriteRAM(0x0000);
LCD_WriteCom(0x00B6); //VSYNC
LCD_WriteRAM((VT>>8)&0X00FF);   //Set VT
LCD_WriteRAM(VT&0X00FF);
LCD_WriteRAM((VPS>>8)&0X00FF);  //Set VPS
LCD_WriteRAM(VPS&0X00FF);
LCD_WriteRAM(VPW);   //Set VPW
LCD_WriteRAM((FPS>>8)&0X00FF);  //Set FPS
LCD_WriteRAM(FPS&0X00FF);
LCD_WriteCom(0x00BA);
LCD_WriteRAM(0x000F);    //GPIO[3:0] out 1
LCD_WriteCom(0x00B8);
LCD_WriteRAM(0x0007);    //GPIO3=input, GPIO[2:0]=output
LCD_WriteRAM(0x0001);    //GPIO0 normal
LCD_WriteCom(0x0036); //rotation
LCD_WriteRAM(0x0008);
LCD_WriteCom(0x00F0); //pixel data interface
LCD_WriteRAM(0x0003);
delay_ms(50);
LCD_WriteCom(0x0029); //display on
LCD_WriteCom(0x00d0);
LCD_WriteRAM(0x000d);
}  
    delay_ms(50);   /* delay 50 ms */
//    LCD_SetFont(&LCD_DEFAULT_FONT);

==================================================================

uint16_t test;

LCD1963_InitIO();

UB_Systick_Pause_ms(10);

LCD1963_InitFSMC ();

UB_Systick_Pause_ms(10);

LCD_Reset_low ();

UB_Systick_Pause_ms(10);

LCD_Reset_high ();

UB_Systick_Pause_ms(10);

LCD1963_WriteCommand (SSD1963_SOFT_RESET );

UB_Systick_Pause_ms(10);

LCD1963_WriteCommand (SSD1963_SET_PLL_MN); // config PLL to 120 Mhz

LCD1963_WriteData (0x23); // 36*10Mhz / 3 = 120 MHz

LCD1963_WriteData (0x02); // N => 36, M => 3

LCD1963_WriteData (0x54);

LCD1963_WriteCommand (SSD1963_SET_PLL);

LCD1963_WriteData (0x01); // enable PLL

UB_Systick_Pause_ms(1); // wait until pll locked

LCD1963_WriteCommand (SSD1963_SET_PLL);

LCD1963_WriteData (0x03);

// set PLL as system clock

LCD1963_WriteCommand (SSD1963_SOFT_RESET );

UB_Systick_Pause_ms(10);

LCD1963_WriteCommand (SSD1963_GET_PLL_STATUS);

test = LCD_RAM; // test = 4 if PLL is locked

UB_Systick_Pause_ms(5);

LCD1963_WriteCommand (SSD1963_SET_LCD_MODE);

LCD1963_WriteData (0x0C); // 18 Bit,  FRC, no Dithering, Vsync, Hsync active low, Data latch @ falling edge

LCD1963_WriteData (0x00); // TFT Mode, Hsync+Vsync+De Mode

LCD1963_WriteData (0x03); // Set horizontal Panel Size = 799 -> 0x31F

LCD1963_WriteData (0x1F);

LCD1963_WriteData (0x01); // Set vertical Panel Size = 479 ->

LCD1963_WriteData (0xDF);

LCD1963_WriteData (0x00);

/////////////////// checked

LCD1963_WriteCommand (SSD1963_SET_PIXEL_DATA_INTERFACE);

LCD1963_WriteData (0x03); // 16 Bit - 565 Format

LCD1963_WriteCommand (SSD1963_SET_LSHIFT_FREQ);

LCD1963_WriteData (0x04); // (Lshiftfrequency / PLLfrequency ) *2^20 = LCDC_FPR

LCD1963_WriteData (0x93); // (40Mhz / 120 MHz ) * 2^20 = 349524 = 0x55554

LCD1963_WriteData (0xE0); //  33Mhz / 120 Mhz ) * 2^20 = 0x46666 alt

/////////////////// checked

LCD1963_WriteCommand (SSD1963_SET_HORI_PERIOD);

LCD1963_WriteData(mHIGH(TFT_HSYNC_PERIOD));

LCD1963_WriteData(mLOW(TFT_HSYNC_PERIOD));

LCD1963_WriteData(mHIGH((TFT_HSYNC_PULSE + TFT_HSYNC_BACK_PORCH)));

LCD1963_WriteData(mLOW((TFT_HSYNC_PULSE + TFT_HSYNC_BACK_PORCH)));

LCD1963_WriteData(TFT_HSYNC_PULSE);

LCD1963_WriteData(0x00);

LCD1963_WriteData(0x00);

LCD1963_WriteData(0x00);

LCD1963_WriteCommand (SSD1963_SET_VERT_PERIOD);

LCD1963_WriteData(mHIGH(TFT_VSYNC_PERIOD));

LCD1963_WriteData(mLOW(TFT_VSYNC_PERIOD));

LCD1963_WriteData(mHIGH((TFT_VSYNC_PULSE + TFT_VSYNC_BACK_PORCH)));

LCD1963_WriteData(mLOW((TFT_VSYNC_PULSE + TFT_VSYNC_BACK_PORCH)));

LCD1963_WriteData(TFT_VSYNC_PULSE);

LCD1963_WriteData(0x00);

LCD1963_WriteData(0x00);

LCD1963_WriteData(0x0060);

LCD1963_WriteCommand(SSD1963_SET_DISPLAY_ON);

UB_Systick_Pause_ms(5);

LCD_Backlight_on ();

======================================================================

STM32F429ZI & SSD1298 & 3.2" TFT LSD GPIO control

main.c

/* Includes ------------------------------------------------------------------*/

#include "main.h"

#include "stm32f4xx_hal.h"

EFM32 UART DMA Tx

#include "em_device.h"
#include "em_chip.h"
#include "em_usart.h"
#include "em_gpio.h"
#include "em_dma.h"
#include "em_cmu.h"
#include "em_emu.h"
#include "em_timer.h"
#include "em_int.h"
#include "em_prs.h"
#include "InitDevice.h"

#define DMA_CHANNEL_UART_TX    0  //
/* DMA init structure */
DMA_Init_TypeDef dmaInit;
/* DMA callback structure */
DMA_CB_TypeDef cb[DMA_CHAN_COUNT];//DMA_CHAN_COUN????
/** DMA control block, requires proper alignment. */
DMA_DESCRIPTOR_TypeDef dmaControlBlock[DMA_CHAN_COUNT * 2] __attribute__ ((aligned(256)));

uint8_t  ucComplete = 0;
uint8_t  Tx_buffer[8] = {0x30,0x31,0x32,0x33,0x34,0x35,0x0D,0x0A};

void UARTTxTransferComplete(unsigned int channel, bool primary, void *user)
{
    ucComplete = 1;
 GPIO_PinOutToggle(gpioPortE, 12);
}

void DMA_for_UART_Tx(void)
{
    DMA_CfgChannel_TypeDef  chnlCfg;
    DMA_CfgDescr_TypeDef    descrCfg;
 
    /* Setting up call-back function */
    cb[DMA_CHANNEL_UART_TX].cbFunc = UARTTxTransferComplete; //Set DMA is completed, whether to call the callback function. If there is no callback function, it is set to NULL
    cb[DMA_CHANNEL_UART_TX].userPtr = NULL;
 
    /* Setting up channel */
    chnlCfg.highPri = false;
    chnlCfg.enableInt = true;
    //Set the DMA to send the next byte of the conditions, here is: When the Tx is completed, DMA then start to take down a byte to send
    chnlCfg.select = DMAREQ_USART1_TXEMPTY;
 
    //Initializes the function of the callback part of the DMA register
    chnlCfg.cb = &(cb[DMA_CHANNEL_UART_TX]);
    DMA_CfgChannel(DMA_CHANNEL_UART_TX, &chnlCfg);
 
    //Register that defines the logical portion of the DMA
    /* Setting up channel descriptor */
    descrCfg.dstInc = dmaDataIncNone;   //Meaning of the target address unchanged
    descrCfg.srcInc = dmaDataInc1;      //This means that the source address is incremented by one byte at a time
    descrCfg.size = dmaDataSize1;       //The byte unit of each transmission
    descrCfg.arbRate = dmaArbitrate1;   //DMA arbitration, one arbitration for every 1 byte sent
    descrCfg.hprot = 0;
    DMA_CfgDescr(DMA_CHANNEL_UART_TX, true, &descrCfg);
}
void DMAInit(void)
{
    CMU_ClockEnable(cmuClock_DMA, true);
  /* Initializing the DMA */
  dmaInit.hprot = 0;
  dmaInit.controlBlock = dmaControlBlock;
  DMA_Init(&dmaInit);
}

int main(void)
{
/* Initialize chip */
CHIP_Init();
enter_DefaultMode_from_RESET();
GPIO_PinModeSet(gpioPortE, 12,  gpioModePushPullDrive, 0); /* TX */
DMAInit();
DMA_for_UART_Tx();
ucComplete = 1;
GPIO_PinOutSet(DE_PORT, DE_PIN);
/* Infinite blink loop */
while(1)
  {
  if(ucComplete)
    {
GPIO_PinOutSet(DE_PORT, DE_PIN);          
    DMA_ActivateBasic(DMA_CHANNEL_UART_TX,
      true,
      false,
      (void *)&(USART1->TXDATA),
      (void *)&Tx_buffer,
      sizeof(Tx_buffer) - 1);
    ucComplete = 0;
    }
  }
}

EFM32 Peripheral Reflex System (PRS)

   PRS позволяет периферийным устройствам общаться друг с другом, без участия процессора, даже когда он находится в состоянии сна. В качестве сигнала используется передача уровня или импульса (level or pulse).

  Producers, consumers and channels (Источники, приемники и каналы)
 
  Перефирийные устройства, которые создают сигналы называют источниками (produsers), а принимающие их приемниками (consumers). PRS для EFM32 в зависимости от серии содержит до 12 каналов для передачи сигналов, каждый из которых может быть подключен к любому источнику и к любому приемнику. Некоторые приемники способны принимать уровень сигнала, но большинство реагирует только на фронт имрульсного сигнала. Канал можно сконфигурировать с помощью emlib функции

 void PRS_SourceSignalSet(unsigned int ch, uint32_t source, uint32_t signal, PRS_Edge_TypeDef  edge)

/***************************************************************************//**
 * @brief
 *   Set source and signal to be used for a channel.
 *
 * @param[in] ch
 *   Channel to define signal and source for.
 *
 * @param[in] source
 *   Source to select for channel. Use one of PRS_CH_CTRL_SOURCESEL_x defines.
 *
 * @param[in] signal
 *   Signal (for selected @p source) to use. Use one of PRS_CH_CTRL_SIGSEL_x
 *   defines.
 *
 * @param[in] edge
 *   Edge (for selected source/signal) to generate pulse for.
 ******************************************************************************/
void PRS_SourceSignalSet(unsigned int ch,
                         uint32_t source,
                         uint32_t signal,
                         PRS_Edge_TypeDef edge)

Эта функция задает PRS каналы по которым будут передавться сигналы между периферийными устройствами. Сигналы можно генерировать и программно с помощью регистров PRS_SWPULSE и PRS_SWLEVEL.

EFM32 Timer frequency meter

// $[TIMER0...3  initialization]
TIMER_Init_TypeDef init = TIMER_INIT_DEFAULT;

init.enable = 1;
init.debugRun = 0;
init.dmaClrAct = 0;
init.sync = 0;
init.clkSel = timerClkSelHFPerClk;
init.prescale = timerPrescale1;
init.fallAction = timerInputActionNone;
init.riseAction = timerInputActionNone;
init.mode = timerModeUp;
init.quadModeX4 = 0;
init.oneShot = 0;
init.count2x = 0;
init.ati = 0;
TIMER_Init(TIMER3, &init);
// [TIMER0...3  initialization]$


// $[TIMER CC0 ... CC2 init]
TIMER_InitCC_TypeDef initCC0 = TIMER_INITCC_DEFAULT;

initCC0.prsInput = false;
initCC0.prsSel = timerPRSSELCh0;
initCC0.edge = timerEdgeRising;
initCC0.mode = timerCCModeOff;
initCC0.eventCtrl = timerEventEveryEdge;
initCC0.filter = 0;
initCC0.cofoa = timerOutputActionNone;
initCC0.cufoa = timerOutputActionNone;
initCC0.cmoa = timerOutputActionNone;
initCC0.coist = 0;
initCC0.outInvert = 0;
TIMER_InitCC(TIMER3, 0, &initCC0);
// [TIMER CC0 ... CC2 init]$

EFM32 Timer pulse generate with & without IRQ

// with IRQ (GPIO output)

/**************************************************************************//**
 * @brief TIMER0_IRQHandler
 * Interrupt Service Routine TIMER0 Interrupt Line
 *****************************************************************************/
void TIMER0_IRQHandler(void)
{
  /* Clear flag for TIMER0 overflow interrupt */
  TIMER_IntClear(TIMER0, TIMER_IF_OF);

  /* Toggle LED ON/OFF */
  GPIO_PinOutToggle(gpioPortC, 0);
}
/**************************************************************************//**
 * @brief  Main function
 * Main is called from __iar_program_start, see assembly startup file
 *****************************************************************************/
int main(void)
{
  /* Initialize chip */
  CHIP_Init();
 
  /* Enable clock for GPIO module */
  CMU_ClockEnable(cmuClock_GPIO, true);

  /* Enable clock for TIMER0 module */
  CMU_ClockEnable(cmuClock_TIMER0, true);

  /* Configure pin as push pull output for LED/pin drive */
  GPIO_PinModeSet(LED_PORT, LED_PIN, gpioModePushPullDrive, 0);

  /* Select TIMER0 parameters */
  TIMER_Init_TypeDef timerInit =
  {
    .enable     = true,
    .debugRun   = true,
    .prescale   = timerPrescale1024,
    .clkSel     = timerClkSelHFPerClk,
    .fallAction = timerInputActionNone,
    .riseAction = timerInputActionNone,
    .mode       = timerModeUp,
    .dmaClrAct  = false,
    .quadModeX4 = false,
    .oneShot    = false,
    .sync       = false,
  };

  /* Enable overflow interrupt */
  TIMER_IntEnable(TIMER0, TIMER_IF_OF);

  /* Enable TIMER0 interrupt vector in NVIC */
  NVIC_EnableIRQ(TIMER0_IRQn);

  /* Set TIMER Top value */
  TIMER_TopSet(TIMER0, TOP);

  /* Configure TIMER */
  TIMER_Init(TIMER0, &timerInit);

  while(1)
  {
    /* Go to EM1 */
    EMU_EnterEM1();
  }

}


//without IRQ (TIMER output)

/**************************************************************************//**
 * @brief  Main function
 * Main is called from __iar_program_start, see assembly startup file
 *****************************************************************************/
int main(void)
{
  /* Initialize chip */
  CHIP_Init();
   
  /* Enable clock for GPIO module */
  CMU_ClockEnable(cmuClock_GPIO, true);
 
  /* Enable clock for TIMER0 module */
  CMU_ClockEnable(cmuClock_TIMER0, true);
 
  /* Set CC0 location 3 pin (PD1) as output */
  GPIO_PinModeSet(gpioPortD, 1, gpioModePushPull, 0);

  /* Select CC channel parameters */
  TIMER_InitCC_TypeDef timerCCInit =
  {
    .cufoa      = timerOutputActionNone,
    .cofoa      = timerOutputActionToggle,
    .cmoa       = timerOutputActionNone,
    .mode       = timerCCModeCompare,
    .filter     = true,
    .prsInput   = false,
    .coist      = false,
    .outInvert  = false,
  };
 
  /* Configure CC channel 0 */
  TIMER_InitCC(TIMER0, 0, &timerCCInit);

  /* Route CC0 to location 3 (PD1) and enable pin */
  TIMER0->ROUTE |= (TIMER_ROUTE_CC0PEN | TIMER_ROUTE_LOCATION_LOC3);
 
  /* Set Top Value */
  TIMER_TopSet(TIMER0, TOP);
 
  /* Select timer parameters */
  TIMER_Init_TypeDef timerInit =
  {
    .enable     = true,
    .debugRun   = true,
    .prescale   = timerPrescale64,
    .clkSel     = timerClkSelHFPerClk,
    .fallAction = timerInputActionNone,
    .riseAction = timerInputActionNone,
    .mode       = timerModeUp,
    .dmaClrAct  = false,
    .quadModeX4 = false,
    .oneShot    = false,
    .sync       = false,
  };
 
  /* Configure timer */
  TIMER_Init(TIMER0, &timerInit);
 
  while(1)
  {
    /* Go to EM1, while TIMER tuns compare output */
    EMU_EnterEM1();
  }
 
}

STM32F ADC with DMA on CMSIS

void DMA2_Stream4_IRQHandler(void)
{
        GPIOD->ODR        ^=((1<<12)|(1<<13)|(1<<14)|(1<<15));
}
uint16_t BUFF[100];int main(void)
{
    SystemInit();
//*********************GPIO*************************
        RCC->AHB1ENR    |= RCC_AHB1ENR_GPIOAEN;
        RCC->AHB1ENR    |= RCC_AHB1ENR_GPIODEN;
        GPIOA->MODER    |= GPIO_MODER_MODER6;        //ADC1 CH6 PA6


//*********************TIM3*************************
        RCC->APB1ENR    |= RCC_APB1ENR_TIM3EN;        // тактирование таймера
        TIM3->PSC         = 160-1;                    // предделитель
        TIM3->ARR         = 1000-1;                    // переполнение
        TIM3->CR2         |= TIM_CR2_MMS_1;            // output (TRGO)
        TIM3->DIER         |= TIM_DIER_UDE;
        TIM3->CR1         |= TIM_CR1_CEN;                //запуск счета


//********************DMA***************************
        RCC->AHB1ENR    |= RCC_AHB1ENR_DMA2EN;
        DMA2_Stream4->CR&=~ DMA_SxCR_CHSEL;            // 000: channel 0 selected
        DMA2_Stream4->PAR= (uint32_t)&ADC1->DR;     //
        DMA2_Stream4->M0AR=(uint32_t)&BUFF[0];        // Массив
        DMA2_Stream4->NDTR=100;                        // Длина буфера
        DMA2_Stream4->CR|= DMA_SxCR_MINC;            // Инкремент адреса
        DMA2_Stream4->CR|= DMA_SxCR_MSIZE_0;        // 16 бит
        DMA2_Stream4->CR|= DMA_SxCR_PSIZE_0;        // 16 бит
        DMA2_Stream4->CR|= DMA_SxCR_CIRC;            // Непрерывный режим
        DMA2_Stream4->CR&=~ DMA_SxCR_DIR;            // 01: peripheral-to-Memory
        DMA2_Stream4->CR|= DMA_SxCR_PL;                // 11: Very high приоритет
        DMA2_Stream4->CR|= DMA_SxCR_TCIE;            // Transfer complete interrupt enable
        DMA2_Stream4->CR|= DMA_SxCR_EN;                 // Вкл. передачу
        NVIC_EnableIRQ(DMA2_Stream4_IRQn);
        NVIC_SetPriority(DMA2_Stream4_IRQn,5);

//********************ADC1**CH6 PA6***************
        RCC->APB2ENR    |= RCC_APB2ENR_ADC1EN;
        ADC1->CR1         |=ADC_CR1_SCAN;                // Scan mode
        ADC1->CR2        |=(ADC_CR2_EXTSEL_3);        //tim 3 (TRGO)
        ADC1->SQR3        =6;                            //выбор канала PA6
        ADC1->CR2         |=ADC_CR2_DMA;                //разрешаем рабуту DMA
        ADC1->CR2         |=ADC_CR2_DDS;                //DMA disable selection (for single ADC mode)
        ADC1->CR2        &=~ADC_CR2_CONT;            //Continuous conversion
        ADC1->CR2        |=ADC_CR2_EXTEN_0;            //01: Trigger detection on the rising edge
        ADC1->CR2        |= ADC_CR2_EOCS;            //разрешаем прерывания
        ADC1->CR2         |=ADC_CR2_ADON;                //Вкл. переобразования