After reset, the FMC bank1 is always enabled to allow boot into external memories. Since
the Cortex®-M7 is doing some speculations, it can generate a speculative read access to
the first FMC bank.
The default FMC configuration being very slow, this speculative access blocks the access to
the FMC by other AHB masters for a very long time, leading to underrun on the LTDC side.
To prevent this CPU speculative read accesses on the FMC bank1, it is recommended to
disable it when it is not used. This can be done by resetting the MBKEN Bit in FMC_BCR1
register which is by default enabled after reset.
To disable the FMC Bank1, the user can use the following code:
/* Disabling FMC Bank1: After reset FMC_BCR1 = 0x000030DB
where MBKEN = 1b meaning that FMC_Bank1 is enabled
and MTYP[1:0]= 10 meaning that memory type is set to NOR Flash/OneNAND
Flash*/
FMC_Bank1->BTCR[0] = 0x000030D2;
For more details on FMC configuration refer to the relevant STM32 reference manual.
the Cortex®-M7 is doing some speculations, it can generate a speculative read access to
the first FMC bank.
The default FMC configuration being very slow, this speculative access blocks the access to
the FMC by other AHB masters for a very long time, leading to underrun on the LTDC side.
To prevent this CPU speculative read accesses on the FMC bank1, it is recommended to
disable it when it is not used. This can be done by resetting the MBKEN Bit in FMC_BCR1
register which is by default enabled after reset.
To disable the FMC Bank1, the user can use the following code:
/* Disabling FMC Bank1: After reset FMC_BCR1 = 0x000030DB
where MBKEN = 1b meaning that FMC_Bank1 is enabled
and MTYP[1:0]= 10 meaning that memory type is set to NOR Flash/OneNAND
Flash*/
FMC_Bank1->BTCR[0] = 0x000030D2;
For more details on FMC configuration refer to the relevant STM32 reference manual.
