CMSIS Library for System Software Reset

/******************************************************************************
 * @file:    core_cm3.h
 * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File
 * @version: V1.20
 * @date:    22. May 2009
 *----------------------------------------------------------------------------
 *
 * Copyright (C) 2009 ARM Limited. All rights reserved.
 *
 * ARM Limited (ARM) is supplying this software for use with Cortex-Mx 
 * processor based microcontrollers.  This file can be freely distributed 
 * within development tools that are supporting such ARM based processors. 
 *
 * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
 *
 ******************************************************************************/

/* memory mapping struct for System Control Block */
typedef struct
{
  __I  uint32_t CPUID;                        /*!< CPU ID Base Register                                     */
  __IO uint32_t ICSR;                         /*!< Interrupt Control State Register                         */
  __IO uint32_t VTOR;                         /*!< Vector Table Offset Register                             */
  __IO uint32_t AIRCR;                        /*!< Application Interrupt / Reset Control Register           */
  __IO uint32_t SCR;                          /*!< System Control Register                                  */
  __IO uint32_t CCR;                          /*!< Configuration Control Register                           */
  __IO uint8_t  SHP[12];                      /*!< System Handlers Priority Registers (4-7, 8-11, 12-15)    */
  __IO uint32_t SHCSR;                        /*!< System Handler Control and State Register                */
  __IO uint32_t CFSR;                         /*!< Configurable Fault Status Register                       */
  __IO uint32_t HFSR;                         /*!< Hard Fault Status Register                                       */
  __IO uint32_t DFSR;                         /*!< Debug Fault Status Register                                          */
  __IO uint32_t MMFAR;                        /*!< Mem Manage Address Register                                  */
  __IO uint32_t BFAR;                         /*!< Bus Fault Address Register                                   */
  __IO uint32_t AFSR;                         /*!< Auxiliary Fault Status Register                              */
  __I  uint32_t PFR[2];                       /*!< Processor Feature Register                               */
  __I  uint32_t DFR;                          /*!< Debug Feature Register                                   */
  __I  uint32_t ADR;                          /*!< Auxiliary Feature Register                               */
  __I  uint32_t MMFR[4];                      /*!< Memory Model Feature Register                            */
  __I  uint32_t ISAR[5];                      /*!< ISA Feature Register                                     */
} SCB_Type;

#define SCS_BASE            (0xE000E000)                              /*!< System Control Space Base Address    */
#define SCB_BASE            (SCS_BASE +  0x0D00)                      /*!< System Control Block Base Address    */
#define SCB                 ((SCB_Type *)           SCB_BASE)         /*!< SCB configuration struct             */

#define NVIC_AIRCR_VECTKEY    (0x5FA << 16)   /*!< AIRCR Key for write access   */
#define NVIC_SYSRESETREQ            2         /*!< System Reset Request         */

/* ##################################    Reset function  ############################################ */
/**
 * @brief  Initiate a system reset request.
 *
 * @param   none
 * @return  none
 *
 * Initialize a system reset request to reset the MCU
 */
static __INLINE void NVIC_SystemReset(void)
{
  SCB->AIRCR  = (NVIC_AIRCR_VECTKEY | (SCB->AIRCR & (0x700)) | (1<<NVIC_SYSRESETREQ)); /* Keep priority group unchanged */
  __DSB();                                                                                 /* Ensure completion of memory access */              
  while(1);                                                                                /* wait until reset */
}

SD Card read in FATFS bug (stm32f7xx_hal_sd.c)

I made project for STM32F746 (LTDC, FMC, SDMMC, FATFS, STemWin + FreeRTOS)

I have problem with reading image file (bmp format) from SD card.

My code



int APP_GetData(void * p, const U8 **ppData, unsigned NumBytesReq, U32 Off){
//You must create an pointer on structure
FIL *phFile;
//and then initialize the pointer value is passed to the function APP_GetData
phFile=(FIL*) p;
//And then use this pointer to your function
f_lseek(phFile,Off);
fresult=f_read(phFile,_acBuffer,NumBytesReq,(void*)&bytesread);
*ppData = _acBuffer;
return bytesread;
}



void picture_test(void){
for(image_number = 1; image_number <= 38;image_number++){
sprintf(st_2,"image%03d",image_number);
sprintf(file_name, "%s%s",st_2,st_3 );
fresult=f_open(&MyFile,file_name, FA_READ);
GUI_MULTIBUF_BeginEx(0);
GUI_BMP_DrawEx(APP_GetData, &MyFile,0,0); // Draw image
GUI_MULTIBUF_EndEx(0);
f_close(&MyFile);
HAL_Delay(1000);
}
}



Code is displays several pictures and stops (HardFault)

Problem solved with correct file stm32f7xx_hal_sd.c



from line 637



/* Empty FIFO if there is still any data */
while ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL)))
{
*tempbuff = SDMMC_ReadFIFO(hsd->Instance);
// tempbuff++;      >>>>>>>>> //  tempbuff++;       !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!         

if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout))
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT;
hsd->State= HAL_SD_STATE_READY;
return HAL_ERROR;
}
}



When I comment line

tempbuff++

I have reading from SD card without HardFault.